/*
 * Copyright (C) 2019 Unigroup Spreadtrum & RDA Technologies Co., Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2019-02-11 15:07:05
 *
 */


#ifndef PUB_QOSC_AHB_REG_H
#define PUB_QOSC_AHB_REG_H

#define CTL_BASE_PUB_QOSC_AHB_REG 0x61020000


#define REG_PUB_QOSC_AHB_REG_QOS_CTRL_EB                    ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0000 )
#define REG_PUB_QOSC_AHB_REG_QOS_CTRL_RESET                 ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0004 )
#define REG_PUB_QOSC_AHB_REG_QOSC_CLK_CTRL                  ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0008 )
#define REG_PUB_QOSC_AHB_REG_QOSC_PORT_ENABLE               ( CTL_BASE_PUB_QOSC_AHB_REG + 0x000C )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_COUNTER_EN             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0010 )
#define REG_PUB_QOSC_AHB_REG_QOSC_AXURGENT_EN               ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0014 )
#define REG_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_EN             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0018 )
#define REG_PUB_QOSC_AHB_REG_QOSC_CFG                       ( CTL_BASE_PUB_QOSC_AHB_REG + 0x001C )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH0  ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0020 )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH1  ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0024 )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH2  ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0028 )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH3  ( CTL_BASE_PUB_QOSC_AHB_REG + 0x002C )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH4  ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0030 )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH5  ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0034 )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH6  ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0038 )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH7  ( CTL_BASE_PUB_QOSC_AHB_REG + 0x003C )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH0  ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0050 )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH1  ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0054 )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH2  ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0058 )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH3  ( CTL_BASE_PUB_QOSC_AHB_REG + 0x005C )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH4  ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0060 )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH5  ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0064 )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH6  ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0068 )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH7  ( CTL_BASE_PUB_QOSC_AHB_REG + 0x006C )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH0       ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0080 )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH1       ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0084 )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH2       ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0088 )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH3       ( CTL_BASE_PUB_QOSC_AHB_REG + 0x008C )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH4       ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0090 )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH5       ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0094 )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH6       ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0098 )
#define REG_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH7       ( CTL_BASE_PUB_QOSC_AHB_REG + 0x009C )
#define REG_PUB_QOSC_AHB_REG_QOSC_BW_TIMING_WINDOW0         ( CTL_BASE_PUB_QOSC_AHB_REG + 0x00B0 )
#define REG_PUB_QOSC_AHB_REG_QOSC_BW_TIMING_WINDOW1         ( CTL_BASE_PUB_QOSC_AHB_REG + 0x00B4 )
#define REG_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_CH0        ( CTL_BASE_PUB_QOSC_AHB_REG + 0x00C0 )
#define REG_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_CH1        ( CTL_BASE_PUB_QOSC_AHB_REG + 0x00C4 )
#define REG_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_CH2        ( CTL_BASE_PUB_QOSC_AHB_REG + 0x00C8 )
#define REG_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_CH3        ( CTL_BASE_PUB_QOSC_AHB_REG + 0x00CC )
#define REG_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_CH4        ( CTL_BASE_PUB_QOSC_AHB_REG + 0x00D0 )
#define REG_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_CH5        ( CTL_BASE_PUB_QOSC_AHB_REG + 0x00D4 )
#define REG_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_CH6        ( CTL_BASE_PUB_QOSC_AHB_REG + 0x00D8 )
#define REG_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_CH7        ( CTL_BASE_PUB_QOSC_AHB_REG + 0x00DC )
#define REG_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_CH8        ( CTL_BASE_PUB_QOSC_AHB_REG + 0x00E0 )
#define REG_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_CH9        ( CTL_BASE_PUB_QOSC_AHB_REG + 0x00E4 )
#define REG_PUB_QOSC_AHB_REG_QOSC_FORCE_URGENT_HIGH_EN      ( CTL_BASE_PUB_QOSC_AHB_REG + 0x00F0 )
#define REG_PUB_QOSC_AHB_REG_QOSC_FORCE_URGENT_ULTRA_EN     ( CTL_BASE_PUB_QOSC_AHB_REG + 0x00F4 )
#define REG_PUB_QOSC_AHB_REG_QOSC_LATMON_AXURGENT_EN        ( CTL_BASE_PUB_QOSC_AHB_REG + 0x00F8 )
#define REG_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_CH0             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0100 )
#define REG_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_CH1             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0104 )
#define REG_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_CH2             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0108 )
#define REG_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_CH3             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x010C )
#define REG_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_CH4             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0110 )
#define REG_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_CH5             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0114 )
#define REG_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_CH6             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0118 )
#define REG_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_CH7             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x011C )
#define REG_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_CH8             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0120 )
#define REG_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_CH9             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0124 )
#define REG_PUB_QOSC_AHB_REG_QOSC_STATUS0                   ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0200 )
#define REG_PUB_QOSC_AHB_REG_QOSC_STATUS1                   ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0204 )
#define REG_PUB_QOSC_AHB_REG_QOSC_STATUS2                   ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0208 )
#define REG_PUB_QOSC_AHB_REG_QOSC_URGENT_COUNT_CH0          ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0210 )
#define REG_PUB_QOSC_AHB_REG_QOSC_URGENT_COUNT_CH1          ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0214 )
#define REG_PUB_QOSC_AHB_REG_QOSC_URGENT_COUNT_CH2          ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0218 )
#define REG_PUB_QOSC_AHB_REG_QOSC_URGENT_COUNT_CH3          ( CTL_BASE_PUB_QOSC_AHB_REG + 0x021C )
#define REG_PUB_QOSC_AHB_REG_QOSC_URGENT_COUNT_CH4          ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0220 )
#define REG_PUB_QOSC_AHB_REG_QOSC_URGENT_COUNT_CH5          ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0224 )
#define REG_PUB_QOSC_AHB_REG_QOSC_URGENT_COUNT_CH6          ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0228 )
#define REG_PUB_QOSC_AHB_REG_QOSC_URGENT_COUNT_CH7          ( CTL_BASE_PUB_QOSC_AHB_REG + 0x022C )
#define REG_PUB_QOSC_AHB_REG_QOSC_DBG_MON                   ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0280 )
#define REG_PUB_QOSC_AHB_REG_QOSC_MON_STATUS                ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0284 )
#define REG_PUB_QOSC_AHB_REG_QOSC_MON_STATUS_1              ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0288 )
#define REG_PUB_QOSC_AHB_REG_LATMON_EB0                     ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0800 )
#define REG_PUB_QOSC_AHB_REG_LATMON_EB1                     ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0804 )
#define REG_PUB_QOSC_AHB_REG_LATMON_RESET                   ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0808 )
#define REG_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_LM0             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x080C )
#define REG_PUB_QOSC_AHB_REG_URGENT_RATIO_LM0               ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0810 )
#define REG_PUB_QOSC_AHB_REG_LATMON_SUB_CFG_LM0             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0814 )
#define REG_PUB_QOSC_AHB_REG_LATMON_HW_DFS_CFG              ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0818 )
#define REG_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_LM1             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0820 )
#define REG_PUB_QOSC_AHB_REG_URGENT_RATIO_LM1               ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0824 )
#define REG_PUB_QOSC_AHB_REG_LATMON_SUB_CFG_LM1             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0828 )
#define REG_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_LM2             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0830 )
#define REG_PUB_QOSC_AHB_REG_URGENT_RATIO_LM2               ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0834 )
#define REG_PUB_QOSC_AHB_REG_LATMON_SUB_CFG_LM2             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0838 )
#define REG_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_LM3             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0840 )
#define REG_PUB_QOSC_AHB_REG_URGENT_RATIO_LM3               ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0844 )
#define REG_PUB_QOSC_AHB_REG_LATMON_SUB_CFG_LM3             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0848 )
#define REG_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_LM4             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0850 )
#define REG_PUB_QOSC_AHB_REG_URGENT_RATIO_LM4               ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0854 )
#define REG_PUB_QOSC_AHB_REG_LATMON_SUB_CFG_LM4             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0858 )
#define REG_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_LM5             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0860 )
#define REG_PUB_QOSC_AHB_REG_URGENT_RATIO_LM5               ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0864 )
#define REG_PUB_QOSC_AHB_REG_LATMON_SUB_CFG_LM5             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0868 )
#define REG_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_LM6             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0870 )
#define REG_PUB_QOSC_AHB_REG_URGENT_RATIO_LM6               ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0874 )
#define REG_PUB_QOSC_AHB_REG_LATMON_SUB_CFG_LM6             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0878 )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM0_STATUS0             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0900 )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM0_STATUS1             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0904 )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM0_STATUS2             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0908 )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM0_STATUS3             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x090C )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM1_STATUS0             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0910 )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM1_STATUS1             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0914 )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM1_STATUS2             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0918 )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM1_STATUS3             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x091C )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM2_STATUS0             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0920 )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM2_STATUS1             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0924 )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM2_STATUS2             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0928 )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM2_STATUS3             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x092C )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM3_STATUS0             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0930 )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM3_STATUS1             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0934 )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM3_STATUS2             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0938 )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM3_STATUS3             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x093C )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM4_STATUS0             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0940 )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM4_STATUS1             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0944 )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM4_STATUS2             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0948 )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM4_STATUS3             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x094C )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM5_STATUS0             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0950 )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM5_STATUS1             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0954 )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM5_STATUS2             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0958 )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM5_STATUS3             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x095C )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM6_STATUS0             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0960 )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM6_STATUS1             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0964 )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM6_STATUS2             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0968 )
#define REG_PUB_QOSC_AHB_REG_LATMON_LM6_STATUS3             ( CTL_BASE_PUB_QOSC_AHB_REG + 0x096C )
#define REG_PUB_QOSC_AHB_REG_LATMON_STATUS0                 ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0970 )
#define REG_PUB_QOSC_AHB_REG_LATMON_STATUS1                 ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0974 )
#define REG_PUB_QOSC_AHB_REG_BWMON_EB                       ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0A00 )
#define REG_PUB_QOSC_AHB_REG_BWMON0_UP_WBW_SET              ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0A04 )
#define REG_PUB_QOSC_AHB_REG_BWMON0_UP_RBW_SET              ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0A08 )
#define REG_PUB_QOSC_AHB_REG_BWMON1_UP_WBW_SET              ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0A0C )
#define REG_PUB_QOSC_AHB_REG_BWMON1_UP_RBW_SET              ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0A10 )
#define REG_PUB_QOSC_AHB_REG_BWMON2_UP_WBW_SET              ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0A14 )
#define REG_PUB_QOSC_AHB_REG_BWMON2_UP_RBW_SET              ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0A18 )
#define REG_PUB_QOSC_AHB_REG_BWMON3_UP_WBW_SET              ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0A1C )
#define REG_PUB_QOSC_AHB_REG_BWMON3_UP_RBW_SET              ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0A20 )
#define REG_PUB_QOSC_AHB_REG_BWMON4_UP_WBW_SET              ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0A24 )
#define REG_PUB_QOSC_AHB_REG_BWMON4_UP_RBW_SET              ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0A28 )
#define REG_PUB_QOSC_AHB_REG_BWMON5_UP_WBW_SET              ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0A2C )
#define REG_PUB_QOSC_AHB_REG_BWMON5_UP_RBW_SET              ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0A30 )
#define REG_PUB_QOSC_AHB_REG_BWMON_STATUS                   ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0A70 )
#define REG_PUB_QOSC_AHB_REG_BWMON0_WBW_CNT                 ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0A80 )
#define REG_PUB_QOSC_AHB_REG_BWMON0_RBW_CNT                 ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0A84 )
#define REG_PUB_QOSC_AHB_REG_BWMON1_WBW_CNT                 ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0A88 )
#define REG_PUB_QOSC_AHB_REG_BWMON1_RBW_CNT                 ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0A8C )
#define REG_PUB_QOSC_AHB_REG_BWMON2_WBW_CNT                 ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0A90 )
#define REG_PUB_QOSC_AHB_REG_BWMON2_RBW_CNT                 ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0A94 )
#define REG_PUB_QOSC_AHB_REG_BWMON3_WBW_CNT                 ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0A98 )
#define REG_PUB_QOSC_AHB_REG_BWMON3_RBW_CNT                 ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0A9C )
#define REG_PUB_QOSC_AHB_REG_BWMON4_WBW_CNT                 ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0AA0 )
#define REG_PUB_QOSC_AHB_REG_BWMON4_RBW_CNT                 ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0AA4 )
#define REG_PUB_QOSC_AHB_REG_BWMON5_WBW_CNT                 ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0AA8 )
#define REG_PUB_QOSC_AHB_REG_BWMON5_RBW_CNT                 ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0AAC )
#define REG_PUB_QOSC_AHB_REG_BWMON_VOTE_CTRL                ( CTL_BASE_PUB_QOSC_AHB_REG + 0x0AB0 )

/* REG_PUB_QOSC_AHB_REG_QOS_CTRL_EB */

#define BIT_PUB_QOSC_AHB_REG_QOS_CTRL_ENABLE                    BIT(0)

/* REG_PUB_QOSC_AHB_REG_QOS_CTRL_RESET */

#define BIT_PUB_QOSC_AHB_REG_QOS_URGENT_COUNT_RESET             BIT(1)
#define BIT_PUB_QOSC_AHB_REG_QOS_CTRL_RESET                     BIT(0)

/* REG_PUB_QOSC_AHB_REG_QOSC_CLK_CTRL */

#define BIT_PUB_QOSC_AHB_REG_QOSC_CFG_CLK_AUTO_GATE_EN          BIT(9)
#define BIT_PUB_QOSC_AHB_REG_QOSC_CFG_CLK_EB                    BIT(8)
#define BIT_PUB_QOSC_AHB_REG_QOSC_CLK_TICK_ENABLE               BIT(4)
#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_LIMIT_AUTO_GATE_EN         BIT(1)
#define BIT_PUB_QOSC_AHB_REG_QOSC_PORT_CLK_AUTO_GATE_EN         BIT(0)

/* REG_PUB_QOSC_AHB_REG_QOSC_PORT_ENABLE */

#define BIT_PUB_QOSC_AHB_REG_QOSC_PORT_ENABLE(x)                (((x) & 0x7F))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_COUNTER_EN */

#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_COUNTER_EN_RD(x)           (((x) & 0x7F) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_COUNTER_EN_WR(x)           (((x) & 0x7F))

/* REG_PUB_QOSC_AHB_REG_QOSC_AXURGENT_EN */

#define BIT_PUB_QOSC_AHB_REG_QOSC_ARURGENT_EN(x)                (((x) & 0x7F) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_AWURGENT_EN(x)                (((x) & 0x7F))

/* REG_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_EN */

#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_EN_RD(x)           (((x) & 0x7F) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_EN_WR(x)           (((x) & 0x7F))

/* REG_PUB_QOSC_AHB_REG_QOSC_CFG */

#define BIT_PUB_QOSC_AHB_REG_QOSC_NO_SV_BW_SLICE_BYPASS         BIT(28)
#define BIT_PUB_QOSC_AHB_REG_QOSC_DFS_FREQ(x)                   (((x) & 0x7) << 24)
#define BIT_PUB_QOSC_AHB_REG_QOSC_DFS_PAUSE_ENABLE              BIT(21)
#define BIT_PUB_QOSC_AHB_REG_QOSC_MODE                          BIT(20)
#define BIT_PUB_QOSC_AHB_REG_QOSC_UG_ULTRA_OSTD_ENABLE          BIT(17)
#define BIT_PUB_QOSC_AHB_REG_QOSC_UG_HIGH_OSTD_ENABLE           BIT(16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_NORM_BYPASS(x)            (((x) & 0x7F))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH0 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_ULTRA_WR_CH0(x)  (((x) & 0x3FF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH0(x)   (((x) & 0x3FF))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH1 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_ULTRA_WR_CH1(x)  (((x) & 0x3FF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH1(x)   (((x) & 0x3FF))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH2 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_ULTRA_WR_CH2(x)  (((x) & 0x3FF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH2(x)   (((x) & 0x3FF))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH3 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_ULTRA_WR_CH3(x)  (((x) & 0x3FF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH3(x)   (((x) & 0x3FF))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH4 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_ULTRA_WR_CH4(x)  (((x) & 0x3FF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH4(x)   (((x) & 0x3FF))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH5 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_ULTRA_WR_CH5(x)  (((x) & 0x3FF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH5(x)   (((x) & 0x3FF))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH6 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_ULTRA_WR_CH6(x)  (((x) & 0x3FF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH6(x)   (((x) & 0x3FF))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_WR_CH7 */


/* REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH0 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_ULTRA_RD_CH0(x)  (((x) & 0x3FF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH0(x)   (((x) & 0x3FF))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH1 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_ULTRA_RD_CH1(x)  (((x) & 0x3FF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH1(x)   (((x) & 0x3FF))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH2 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_ULTRA_RD_CH2(x)  (((x) & 0x3FF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH2(x)   (((x) & 0x3FF))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH3 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_ULTRA_RD_CH3(x)  (((x) & 0x3FF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH3(x)   (((x) & 0x3FF))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH4 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_ULTRA_RD_CH4(x)  (((x) & 0x3FF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH4(x)   (((x) & 0x3FF))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH5 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_ULTRA_RD_CH5(x)  (((x) & 0x3FF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH5(x)   (((x) & 0x3FF))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH6 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_ULTRA_RD_CH6(x)  (((x) & 0x3FF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH6(x)   (((x) & 0x3FF))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_THRESHOLD_HIGH_RD_CH7 */


/* REG_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH0 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH0(x)        (((x) & 0x3F))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH1 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH1(x)        (((x) & 0x3F))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH2 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH2(x)        (((x) & 0x3F))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH3 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH3(x)        (((x) & 0x3F))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH4 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH4(x)        (((x) & 0x3F))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH5 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH5(x)        (((x) & 0x3F))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH6 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH6(x)        (((x) & 0x3F))

/* REG_PUB_QOSC_AHB_REG_QOSC_SV_COUNT_OFFSET_CH7 */


/* REG_PUB_QOSC_AHB_REG_QOSC_BW_TIMING_WINDOW0 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_TIMING_WINDOW_CH7(x)       (((x) & 0x7) << 28)
#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_TIMING_WINDOW_CH6(x)       (((x) & 0x7) << 24)
#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_TIMING_WINDOW_CH5(x)       (((x) & 0x7) << 20)
#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_TIMING_WINDOW_CH4(x)       (((x) & 0x7) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_TIMING_WINDOW_CH3(x)       (((x) & 0x7) << 12)
#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_TIMING_WINDOW_CH2(x)       (((x) & 0x7) << 8)
#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_TIMING_WINDOW_CH1(x)       (((x) & 0x7) << 4)
#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_TIMING_WINDOW_CH0(x)       (((x) & 0x7))

/* REG_PUB_QOSC_AHB_REG_QOSC_BW_TIMING_WINDOW1 */


/* REG_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_CH0 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_RD_CH0(x)      (((x) & 0xFF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_WR_CH0(x)      (((x) & 0xFF))

/* REG_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_CH1 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_RD_CH1(x)      (((x) & 0xFF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_WR_CH1(x)      (((x) & 0xFF))

/* REG_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_CH2 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_RD_CH2(x)      (((x) & 0xFF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_WR_CH2(x)      (((x) & 0xFF))

/* REG_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_CH3 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_RD_CH3(x)      (((x) & 0xFF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_WR_CH3(x)      (((x) & 0xFF))

/* REG_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_CH4 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_RD_CH4(x)      (((x) & 0xFF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_WR_CH4(x)      (((x) & 0xFF))

/* REG_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_CH5 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_RD_CH5(x)      (((x) & 0xFF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_WR_CH5(x)      (((x) & 0xFF))

/* REG_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_CH6 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_RD_CH6(x)      (((x) & 0xFF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_WR_CH6(x)      (((x) & 0xFF))

/* REG_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_CH7 */


/* REG_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_CH8 */


/* REG_PUB_QOSC_AHB_REG_QOSC_BW_LIMITER_MAX_CH9 */


/* REG_PUB_QOSC_AHB_REG_QOSC_FORCE_URGENT_HIGH_EN */

#define BIT_PUB_QOSC_AHB_REG_QOSC_FORCE_URGENT_HIGH_EN_RD(x)    (((x) & 0x7F) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_FORCE_URGENT_HIGH_EN_WR(x)    (((x) & 0x7F))

/* REG_PUB_QOSC_AHB_REG_QOSC_FORCE_URGENT_ULTRA_EN */

#define BIT_PUB_QOSC_AHB_REG_QOSC_FORCE_URGENT_ULTRA_EN_RD(x)   (((x) & 0x7F) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_FORCE_URGENT_ULTRA_EN_WR(x)   (((x) & 0x7F))

/* REG_PUB_QOSC_AHB_REG_QOSC_LATMON_AXURGENT_EN */

#define BIT_PUB_QOSC_AHB_REG_QOSC_LATMON_ARURGENT_EN(x)         (((x) & 0x7F) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_LATMON_AWURGENT_EN(x)         (((x) & 0x7F))

/* REG_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_CH0 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_ULTRA_RD_CH0(x)     (((x) & 0xF) << 28)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_ULTRA_WR_CH0(x)     (((x) & 0xF) << 24)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_HIGH_RD_CH0(x)      (((x) & 0xF) << 20)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_HIGH_WR_CH0(x)      (((x) & 0xF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_NORM_RD_CH0(x)      (((x) & 0xF) << 12)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_NORM_WR_CH0(x)      (((x) & 0xF) << 8)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_LOW_RD_CH0(x)       (((x) & 0xF) << 4)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_LOW_WR_CH0(x)       (((x) & 0xF))

/* REG_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_CH1 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_ULTRA_RD_CH1(x)     (((x) & 0xF) << 28)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_ULTRA_WR_CH1(x)     (((x) & 0xF) << 24)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_HIGH_RD_CH1(x)      (((x) & 0xF) << 20)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_HIGH_WR_CH1(x)      (((x) & 0xF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_NORM_RD_CH1(x)      (((x) & 0xF) << 12)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_NORM_WR_CH1(x)      (((x) & 0xF) << 8)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_LOW_RD_CH1(x)       (((x) & 0xF) << 4)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_LOW_WR_CH1(x)       (((x) & 0xF))

/* REG_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_CH2 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_ULTRA_RD_CH2(x)     (((x) & 0xF) << 28)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_ULTRA_WR_CH2(x)     (((x) & 0xF) << 24)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_HIGH_RD_CH2(x)      (((x) & 0xF) << 20)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_HIGH_WR_CH2(x)      (((x) & 0xF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_NORM_RD_CH2(x)      (((x) & 0xF) << 12)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_NORM_WR_CH2(x)      (((x) & 0xF) << 8)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_LOW_RD_CH2(x)       (((x) & 0xF) << 4)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_LOW_WR_CH2(x)       (((x) & 0xF))

/* REG_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_CH3 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_ULTRA_RD_CH3(x)     (((x) & 0xF) << 28)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_ULTRA_WR_CH3(x)     (((x) & 0xF) << 24)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_HIGH_RD_CH3(x)      (((x) & 0xF) << 20)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_HIGH_WR_CH3(x)      (((x) & 0xF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_NORM_RD_CH3(x)      (((x) & 0xF) << 12)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_NORM_WR_CH3(x)      (((x) & 0xF) << 8)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_LOW_RD_CH3(x)       (((x) & 0xF) << 4)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_LOW_WR_CH3(x)       (((x) & 0xF))

/* REG_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_CH4 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_ULTRA_RD_CH4(x)     (((x) & 0xF) << 28)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_ULTRA_WR_CH4(x)     (((x) & 0xF) << 24)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_HIGH_RD_CH4(x)      (((x) & 0xF) << 20)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_HIGH_WR_CH4(x)      (((x) & 0xF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_NORM_RD_CH4(x)      (((x) & 0xF) << 12)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_NORM_WR_CH4(x)      (((x) & 0xF) << 8)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_LOW_RD_CH4(x)       (((x) & 0xF) << 4)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_LOW_WR_CH4(x)       (((x) & 0xF))

/* REG_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_CH5 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_ULTRA_RD_CH5(x)     (((x) & 0xF) << 28)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_ULTRA_WR_CH5(x)     (((x) & 0xF) << 24)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_HIGH_RD_CH5(x)      (((x) & 0xF) << 20)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_HIGH_WR_CH5(x)      (((x) & 0xF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_NORM_RD_CH5(x)      (((x) & 0xF) << 12)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_NORM_WR_CH5(x)      (((x) & 0xF) << 8)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_LOW_RD_CH5(x)       (((x) & 0xF) << 4)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_LOW_WR_CH5(x)       (((x) & 0xF))

/* REG_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_CH6 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_ULTRA_RD_CH6(x)     (((x) & 0xF) << 28)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_ULTRA_WR_CH6(x)     (((x) & 0xF) << 24)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_HIGH_RD_CH6(x)      (((x) & 0xF) << 20)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_HIGH_WR_CH6(x)      (((x) & 0xF) << 16)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_NORM_RD_CH6(x)      (((x) & 0xF) << 12)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_NORM_WR_CH6(x)      (((x) & 0xF) << 8)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_LOW_RD_CH6(x)       (((x) & 0xF) << 4)
#define BIT_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_LOW_WR_CH6(x)       (((x) & 0xF))

/* REG_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_CH7 */


/* REG_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_CH8 */


/* REG_PUB_QOSC_AHB_REG_QOSC_QOS_VALUE_CH9 */


/* REG_PUB_QOSC_AHB_REG_QOSC_STATUS0 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_STATUS0(x)                    (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_QOSC_STATUS1 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_STATUS1(x)                    (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_QOSC_STATUS2 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_STATUS2(x)                    (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_QOSC_URGENT_COUNT_CH0 */

#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_COUNT_RD_CH0(x)       (((x) & 0xFF) << 24)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_COUNT_RD_CH0(x)        (((x) & 0xFF) << 16)
#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_COUNT_WR_CH0(x)       (((x) & 0xFF) << 8)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_COUNT_WR_CH0(x)        (((x) & 0xFF))

/* REG_PUB_QOSC_AHB_REG_QOSC_URGENT_COUNT_CH1 */

#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_COUNT_RD_CH1(x)       (((x) & 0xFF) << 24)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_COUNT_RD_CH1(x)        (((x) & 0xFF) << 16)
#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_COUNT_WR_CH1(x)       (((x) & 0xFF) << 8)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_COUNT_WR_CH1(x)        (((x) & 0xFF))

/* REG_PUB_QOSC_AHB_REG_QOSC_URGENT_COUNT_CH2 */

#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_COUNT_RD_CH2(x)       (((x) & 0xFF) << 24)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_COUNT_RD_CH2(x)        (((x) & 0xFF) << 16)
#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_COUNT_WR_CH2(x)       (((x) & 0xFF) << 8)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_COUNT_WR_CH2(x)        (((x) & 0xFF))

/* REG_PUB_QOSC_AHB_REG_QOSC_URGENT_COUNT_CH3 */

#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_COUNT_RD_CH3(x)       (((x) & 0xFF) << 24)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_COUNT_RD_CH3(x)        (((x) & 0xFF) << 16)
#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_COUNT_WR_CH3(x)       (((x) & 0xFF) << 8)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_COUNT_WR_CH3(x)        (((x) & 0xFF))

/* REG_PUB_QOSC_AHB_REG_QOSC_URGENT_COUNT_CH4 */

#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_COUNT_RD_CH4(x)       (((x) & 0xFF) << 24)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_COUNT_RD_CH4(x)        (((x) & 0xFF) << 16)
#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_COUNT_WR_CH4(x)       (((x) & 0xFF) << 8)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_COUNT_WR_CH4(x)        (((x) & 0xFF))

/* REG_PUB_QOSC_AHB_REG_QOSC_URGENT_COUNT_CH5 */

#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_COUNT_RD_CH5(x)       (((x) & 0xFF) << 24)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_COUNT_RD_CH5(x)        (((x) & 0xFF) << 16)
#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_COUNT_WR_CH5(x)       (((x) & 0xFF) << 8)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_COUNT_WR_CH5(x)        (((x) & 0xFF))

/* REG_PUB_QOSC_AHB_REG_QOSC_URGENT_COUNT_CH6 */

#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_COUNT_RD_CH6(x)       (((x) & 0xFF) << 24)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_COUNT_RD_CH6(x)        (((x) & 0xFF) << 16)
#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_COUNT_WR_CH6(x)       (((x) & 0xFF) << 8)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_COUNT_WR_CH6(x)        (((x) & 0xFF))

/* REG_PUB_QOSC_AHB_REG_QOSC_URGENT_COUNT_CH7 */


/* REG_PUB_QOSC_AHB_REG_QOSC_DBG_MON */

#define BIT_PUB_QOSC_AHB_REG_QOS_DBG_MON_SEL(x)                 (((x) & 0xF) << 4)
#define BIT_PUB_QOSC_AHB_REG_QOS_DBG_MON_EB                     BIT(1)
#define BIT_PUB_QOSC_AHB_REG_QOS_DBG_MON_START                  BIT(0)

/* REG_PUB_QOSC_AHB_REG_QOSC_MON_STATUS */

#define BIT_PUB_QOSC_AHB_REG_QOSC_MON_STATUS(x)                 (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_QOSC_MON_STATUS_1 */

#define BIT_PUB_QOSC_AHB_REG_QOSC_MON_OVERFLOW_CNT(x)           (((x) & 0x1F))

/* REG_PUB_QOSC_AHB_REG_LATMON_EB0 */

#define BIT_PUB_QOSC_AHB_REG_LATMON_SW_TIMER_EN(x)              (((x) & 0x7F) << 16)
#define BIT_PUB_QOSC_AHB_REG_LATMON_TIMER_SEL(x)                (((x) & 0x7F))

/* REG_PUB_QOSC_AHB_REG_LATMON_EB1 */

#define BIT_PUB_QOSC_AHB_REG_LATMON2_SEL                        BIT(23)
#define BIT_PUB_QOSC_AHB_REG_LATMON_AUTO_GATE_EN(x)             (((x) & 0x7F) << 16)
#define BIT_PUB_QOSC_AHB_REG_LATMON_CLK_TICK_ENABLE(x)          (((x) & 0x7F) << 8)
#define BIT_PUB_QOSC_AHB_REG_LATMON_ENABLE(x)                   (((x) & 0x7F))

/* REG_PUB_QOSC_AHB_REG_LATMON_RESET */

#define BIT_PUB_QOSC_AHB_REG_LATMON_COUNT_RESET(x)              (((x) & 0x7F) << 8)
#define BIT_PUB_QOSC_AHB_REG_LATMON_RESET(x)                    (((x) & 0x7F))

/* REG_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_LM0 */

#define BIT_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_RD_LM0(x)           (((x) & 0xFF) << 16)
#define BIT_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_WR_LM0(x)           (((x) & 0xFF))

/* REG_PUB_QOSC_AHB_REG_URGENT_RATIO_LM0 */

#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_RATIO_RD_LM0(x)       (((x) & 0x3) << 12)
#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_RATIO_WR_LM0(x)       (((x) & 0x3) << 8)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_RATIO_RD_LM0(x)        (((x) & 0x3) << 4)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_RATIO_WR_LM0(x)        (((x) & 0x3))

/* REG_PUB_QOSC_AHB_REG_LATMON_SUB_CFG_LM0 */

#define BIT_PUB_QOSC_AHB_REG_LATMON_INIT_URGENT_DEB_LM0(x)      (((x) & 0x7) << 28)
#define BIT_PUB_QOSC_AHB_REG_TIMER_LAT_SUB_SEL_LM0(x)           (((x) & 0x3) << 26)
#define BIT_PUB_QOSC_AHB_REG_TIMER_LAT_SUB_VALUE_LM0(x)         (((x) & 0xFFF) << 12)
#define BIT_PUB_QOSC_AHB_REG_LAT_SUB_ALL_RATIO_LM0(x)           (((x) & 0x3) << 8)
#define BIT_PUB_QOSC_AHB_REG_TIMER_LAT_SUB_PERIOD_LM0(x)        (((x) & 0xF))

/* REG_PUB_QOSC_AHB_REG_LATMON_HW_DFS_CFG */

#define BIT_PUB_QOSC_AHB_REG_LATMON_HW_DFS_TRIGGER_SEL_LM6(x)   (((x) & 0x7) << 28)
#define BIT_PUB_QOSC_AHB_REG_LATMON_HW_DFS_TRIGGER_SEL_LM5(x)   (((x) & 0x7) << 25)
#define BIT_PUB_QOSC_AHB_REG_LATMON_HW_DFS_TRIGGER_SEL_LM4(x)   (((x) & 0x7) << 22)
#define BIT_PUB_QOSC_AHB_REG_LATMON_HW_DFS_TRIGGER_SEL_LM3(x)   (((x) & 0x7) << 19)
#define BIT_PUB_QOSC_AHB_REG_LATMON_HW_DFS_TRIGGER_SEL_LM2(x)   (((x) & 0x7) << 16)
#define BIT_PUB_QOSC_AHB_REG_LATMON_HW_DFS_TRIGGER_SEL_LM1(x)   (((x) & 0x7) << 12)
#define BIT_PUB_QOSC_AHB_REG_LATMON_HW_DFS_TRIGGER_SEL_LM0(x)   (((x) & 0x7) << 8)
#define BIT_PUB_QOSC_AHB_REG_LATMON_HW_DFS_TRIGGER_EN(x)        (((x) & 0x7F))

/* REG_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_LM1 */

#define BIT_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_RD_LM1(x)           (((x) & 0xFF) << 16)
#define BIT_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_WR_LM1(x)           (((x) & 0xFF))

/* REG_PUB_QOSC_AHB_REG_URGENT_RATIO_LM1 */

#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_RATIO_RD_LM1(x)       (((x) & 0x3) << 12)
#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_RATIO_WR_LM1(x)       (((x) & 0x3) << 8)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_RATIO_RD_LM1(x)        (((x) & 0x3) << 4)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_RATIO_WR_LM1(x)        (((x) & 0x3))

/* REG_PUB_QOSC_AHB_REG_LATMON_SUB_CFG_LM1 */

#define BIT_PUB_QOSC_AHB_REG_LATMON_INIT_URGENT_DEB_LM1(x)      (((x) & 0x7) << 28)
#define BIT_PUB_QOSC_AHB_REG_TIMER_LAT_SUB_SEL_LM1(x)           (((x) & 0x3) << 26)
#define BIT_PUB_QOSC_AHB_REG_TIMER_LAT_SUB_VALUE_LM1(x)         (((x) & 0xFFF) << 12)
#define BIT_PUB_QOSC_AHB_REG_LAT_SUB_ALL_RATIO_LM1(x)           (((x) & 0x3) << 8)
#define BIT_PUB_QOSC_AHB_REG_TIMER_LAT_SUB_PERIOD_LM1(x)        (((x) & 0xF))

/* REG_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_LM2 */

#define BIT_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_RD_LM2(x)           (((x) & 0xFF) << 16)
#define BIT_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_WR_LM2(x)           (((x) & 0xFF))

/* REG_PUB_QOSC_AHB_REG_URGENT_RATIO_LM2 */

#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_RATIO_RD_LM2(x)       (((x) & 0x3) << 12)
#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_RATIO_WR_LM2(x)       (((x) & 0x3) << 8)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_RATIO_RD_LM2(x)        (((x) & 0x3) << 4)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_RATIO_WR_LM2(x)        (((x) & 0x3))

/* REG_PUB_QOSC_AHB_REG_LATMON_SUB_CFG_LM2 */

#define BIT_PUB_QOSC_AHB_REG_LATMON_INIT_URGENT_DEB_LM2(x)      (((x) & 0x7) << 28)
#define BIT_PUB_QOSC_AHB_REG_TIMER_LAT_SUB_SEL_LM2(x)           (((x) & 0x3) << 26)
#define BIT_PUB_QOSC_AHB_REG_TIMER_LAT_SUB_VALUE_LM2(x)         (((x) & 0xFFF) << 12)
#define BIT_PUB_QOSC_AHB_REG_LAT_SUB_ALL_RATIO_LM2(x)           (((x) & 0x3) << 8)
#define BIT_PUB_QOSC_AHB_REG_TIMER_LAT_SUB_PERIOD_LM2(x)        (((x) & 0xF))

/* REG_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_LM3 */

#define BIT_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_RD_LM3(x)           (((x) & 0xFF) << 16)
#define BIT_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_WR_LM3(x)           (((x) & 0xFF))

/* REG_PUB_QOSC_AHB_REG_URGENT_RATIO_LM3 */

#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_RATIO_RD_LM3(x)       (((x) & 0x3) << 12)
#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_RATIO_WR_LM3(x)       (((x) & 0x3) << 8)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_RATIO_RD_LM3(x)        (((x) & 0x3) << 4)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_RATIO_WR_LM3(x)        (((x) & 0x3))

/* REG_PUB_QOSC_AHB_REG_LATMON_SUB_CFG_LM3 */

#define BIT_PUB_QOSC_AHB_REG_LATMON_INIT_URGENT_DEB_LM3(x)      (((x) & 0x7) << 28)
#define BIT_PUB_QOSC_AHB_REG_TIMER_LAT_SUB_SEL_LM3(x)           (((x) & 0x3) << 26)
#define BIT_PUB_QOSC_AHB_REG_TIMER_LAT_SUB_VALUE_LM3(x)         (((x) & 0xFFF) << 12)
#define BIT_PUB_QOSC_AHB_REG_LAT_SUB_ALL_RATIO_LM3(x)           (((x) & 0x3) << 8)
#define BIT_PUB_QOSC_AHB_REG_TIMER_LAT_SUB_PERIOD_LM3(x)        (((x) & 0xF))

/* REG_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_LM4 */

#define BIT_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_RD_LM4(x)           (((x) & 0xFF) << 16)
#define BIT_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_WR_LM4(x)           (((x) & 0xFF))

/* REG_PUB_QOSC_AHB_REG_URGENT_RATIO_LM4 */

#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_RATIO_RD_LM4(x)       (((x) & 0x3) << 12)
#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_RATIO_WR_LM4(x)       (((x) & 0x3) << 8)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_RATIO_RD_LM4(x)        (((x) & 0x3) << 4)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_RATIO_WR_LM4(x)        (((x) & 0x3))

/* REG_PUB_QOSC_AHB_REG_LATMON_SUB_CFG_LM4 */

#define BIT_PUB_QOSC_AHB_REG_LATMON_INIT_URGENT_DEB_LM4(x)      (((x) & 0x7) << 28)
#define BIT_PUB_QOSC_AHB_REG_TIMER_LAT_SUB_SEL_LM4(x)           (((x) & 0x3) << 26)
#define BIT_PUB_QOSC_AHB_REG_TIMER_LAT_SUB_VALUE_LM4(x)         (((x) & 0xFFF) << 12)
#define BIT_PUB_QOSC_AHB_REG_LAT_SUB_ALL_RATIO_LM4(x)           (((x) & 0x3) << 8)
#define BIT_PUB_QOSC_AHB_REG_TIMER_LAT_SUB_PERIOD_LM4(x)        (((x) & 0xF))

/* REG_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_LM5 */

#define BIT_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_RD_LM5(x)           (((x) & 0xFF) << 16)
#define BIT_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_WR_LM5(x)           (((x) & 0xFF))

/* REG_PUB_QOSC_AHB_REG_URGENT_RATIO_LM5 */

#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_RATIO_RD_LM5(x)       (((x) & 0x3) << 12)
#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_RATIO_WR_LM5(x)       (((x) & 0x3) << 8)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_RATIO_RD_LM5(x)        (((x) & 0x3) << 4)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_RATIO_WR_LM5(x)        (((x) & 0x3))

/* REG_PUB_QOSC_AHB_REG_LATMON_SUB_CFG_LM5 */

#define BIT_PUB_QOSC_AHB_REG_LATMON_INIT_URGENT_DEB_LM5(x)      (((x) & 0x7) << 28)
#define BIT_PUB_QOSC_AHB_REG_TIMER_LAT_SUB_SEL_LM5(x)           (((x) & 0x3) << 26)
#define BIT_PUB_QOSC_AHB_REG_TIMER_LAT_SUB_VALUE_LM5(x)         (((x) & 0xFFF) << 12)
#define BIT_PUB_QOSC_AHB_REG_LAT_SUB_ALL_RATIO_LM5(x)           (((x) & 0x3) << 8)
#define BIT_PUB_QOSC_AHB_REG_TIMER_LAT_SUB_PERIOD_LM5(x)        (((x) & 0xF))

/* REG_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_LM6 */

#define BIT_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_RD_LM6(x)           (((x) & 0xFF) << 16)
#define BIT_PUB_QOSC_AHB_REG_TAR_LAT_OFFSET_WR_LM6(x)           (((x) & 0xFF))

/* REG_PUB_QOSC_AHB_REG_URGENT_RATIO_LM6 */

#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_RATIO_RD_LM6(x)       (((x) & 0x3) << 12)
#define BIT_PUB_QOSC_AHB_REG_URGENT_ULTRA_RATIO_WR_LM6(x)       (((x) & 0x3) << 8)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_RATIO_RD_LM6(x)        (((x) & 0x3) << 4)
#define BIT_PUB_QOSC_AHB_REG_URGENT_HIGH_RATIO_WR_LM6(x)        (((x) & 0x3))

/* REG_PUB_QOSC_AHB_REG_LATMON_SUB_CFG_LM6 */

#define BIT_PUB_QOSC_AHB_REG_LATMON_INIT_URGENT_DEB_LM6(x)      (((x) & 0x7) << 28)
#define BIT_PUB_QOSC_AHB_REG_TIMER_LAT_SUB_SEL_LM6(x)           (((x) & 0x3) << 26)
#define BIT_PUB_QOSC_AHB_REG_TIMER_LAT_SUB_VALUE_LM6(x)         (((x) & 0xFFF) << 12)
#define BIT_PUB_QOSC_AHB_REG_LAT_SUB_ALL_RATIO_LM6(x)           (((x) & 0x3) << 8)
#define BIT_PUB_QOSC_AHB_REG_TIMER_LAT_SUB_PERIOD_LM6(x)        (((x) & 0xF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM0_STATUS0 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_ACTUAL_WR_LM0(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM0_STATUS1 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_TARGET_WR_LM0(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM0_STATUS2 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_ACTUAL_RD_LM0(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM0_STATUS3 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_TARGET_RD_LM0(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM1_STATUS0 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_ACTUAL_WR_LM1(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM1_STATUS1 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_TARGET_WR_LM1(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM1_STATUS2 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_ACTUAL_RD_LM1(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM1_STATUS3 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_TARGET_RD_LM1(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM2_STATUS0 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_ACTUAL_WR_LM2(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM2_STATUS1 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_TARGET_WR_LM2(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM2_STATUS2 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_ACTUAL_RD_LM2(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM2_STATUS3 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_TARGET_RD_LM2(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM3_STATUS0 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_ACTUAL_WR_LM3(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM3_STATUS1 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_TARGET_WR_LM3(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM3_STATUS2 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_ACTUAL_RD_LM3(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM3_STATUS3 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_TARGET_RD_LM3(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM4_STATUS0 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_ACTUAL_WR_LM4(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM4_STATUS1 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_TARGET_WR_LM4(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM4_STATUS2 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_ACTUAL_RD_LM4(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM4_STATUS3 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_TARGET_RD_LM4(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM5_STATUS0 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_ACTUAL_WR_LM5(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM5_STATUS1 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_TARGET_WR_LM5(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM5_STATUS2 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_ACTUAL_RD_LM5(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM5_STATUS3 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_TARGET_RD_LM5(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM6_STATUS0 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_ACTUAL_WR_LM6(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM6_STATUS1 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_TARGET_WR_LM6(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM6_STATUS2 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_ACTUAL_RD_LM6(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_LM6_STATUS3 */

#define BIT_PUB_QOSC_AHB_REG_LATENCY_TARGET_RD_LM6(x)           (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_LATMON_STATUS0 */

#define BIT_PUB_QOSC_AHB_REG_LATMON6_UPDATE_FLAG_CLR            BIT(14)
#define BIT_PUB_QOSC_AHB_REG_LATMON5_UPDATE_FLAG_CLR            BIT(13)
#define BIT_PUB_QOSC_AHB_REG_LATMON4_UPDATE_FLAG_CLR            BIT(12)
#define BIT_PUB_QOSC_AHB_REG_LATMON3_UPDATE_FLAG_CLR            BIT(11)
#define BIT_PUB_QOSC_AHB_REG_LATMON2_UPDATE_FLAG_CLR            BIT(10)
#define BIT_PUB_QOSC_AHB_REG_LATMON1_UPDATE_FLAG_CLR            BIT(9)
#define BIT_PUB_QOSC_AHB_REG_LATMON0_UPDATE_FLAG_CLR            BIT(8)
#define BIT_PUB_QOSC_AHB_REG_LATMON6_UPDATE_FLAG                BIT(6)
#define BIT_PUB_QOSC_AHB_REG_LATMON5_UPDATE_FLAG                BIT(5)
#define BIT_PUB_QOSC_AHB_REG_LATMON4_UPDATE_FLAG                BIT(4)
#define BIT_PUB_QOSC_AHB_REG_LATMON3_UPDATE_FLAG                BIT(3)
#define BIT_PUB_QOSC_AHB_REG_LATMON2_UPDATE_FLAG                BIT(2)
#define BIT_PUB_QOSC_AHB_REG_LATMON1_UPDATE_FLAG                BIT(1)
#define BIT_PUB_QOSC_AHB_REG_LATMON0_UPDATE_FLAG                BIT(0)

/* REG_PUB_QOSC_AHB_REG_LATMON_STATUS1 */

#define BIT_PUB_QOSC_AHB_REG_LATMON_COUNTER_OV_ST(x)            (((x) & 0xFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON_EB */

#define BIT_PUB_QOSC_AHB_REG_BWMON_F_UP_REQ_EN(x)               (((x) & 0x3F) << 24)
#define BIT_PUB_QOSC_AHB_REG_BWMON_RBW_EN(x)                    (((x) & 0x3F) << 16)
#define BIT_PUB_QOSC_AHB_REG_BWMON_WBW_EN(x)                    (((x) & 0x3F) << 8)
#define BIT_PUB_QOSC_AHB_REG_BWMON_ENABLE(x)                    (((x) & 0x3F))

/* REG_PUB_QOSC_AHB_REG_BWMON0_UP_WBW_SET */

#define BIT_PUB_QOSC_AHB_REG_BWMON0_UP_WBW_SET(x)               (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON0_UP_RBW_SET */

#define BIT_PUB_QOSC_AHB_REG_BWMON0_UP_RBW_SET(x)               (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON1_UP_WBW_SET */

#define BIT_PUB_QOSC_AHB_REG_BWMON1_UP_WBW_SET(x)               (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON1_UP_RBW_SET */

#define BIT_PUB_QOSC_AHB_REG_BWMON1_UP_RBW_SET(x)               (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON2_UP_WBW_SET */

#define BIT_PUB_QOSC_AHB_REG_BWMON2_UP_WBW_SET(x)               (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON2_UP_RBW_SET */

#define BIT_PUB_QOSC_AHB_REG_BWMON2_UP_RBW_SET(x)               (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON3_UP_WBW_SET */

#define BIT_PUB_QOSC_AHB_REG_BWMON3_UP_WBW_SET(x)               (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON3_UP_RBW_SET */

#define BIT_PUB_QOSC_AHB_REG_BWMON3_UP_RBW_SET(x)               (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON4_UP_WBW_SET */

#define BIT_PUB_QOSC_AHB_REG_BWMON4_UP_WBW_SET(x)               (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON4_UP_RBW_SET */

#define BIT_PUB_QOSC_AHB_REG_BWMON4_UP_RBW_SET(x)               (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON5_UP_WBW_SET */

#define BIT_PUB_QOSC_AHB_REG_BWMON5_UP_WBW_SET(x)               (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON5_UP_RBW_SET */

#define BIT_PUB_QOSC_AHB_REG_BWMON5_UP_RBW_SET(x)               (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON_STATUS */

#define BIT_PUB_QOSC_AHB_REG_BWMON5_UPDATE_FLAG_CLR             BIT(13)
#define BIT_PUB_QOSC_AHB_REG_BWMON4_UPDATE_FLAG_CLR             BIT(12)
#define BIT_PUB_QOSC_AHB_REG_BWMON3_UPDATE_FLAG_CLR             BIT(11)
#define BIT_PUB_QOSC_AHB_REG_BWMON2_UPDATE_FLAG_CLR             BIT(10)
#define BIT_PUB_QOSC_AHB_REG_BWMON1_UPDATE_FLAG_CLR             BIT(9)
#define BIT_PUB_QOSC_AHB_REG_BWMON0_UPDATE_FLAG_CLR             BIT(8)
#define BIT_PUB_QOSC_AHB_REG_BWMON5_UPDATE_FLAG                 BIT(5)
#define BIT_PUB_QOSC_AHB_REG_BWMON4_UPDATE_FLAG                 BIT(4)
#define BIT_PUB_QOSC_AHB_REG_BWMON3_UPDATE_FLAG                 BIT(3)
#define BIT_PUB_QOSC_AHB_REG_BWMON2_UPDATE_FLAG                 BIT(2)
#define BIT_PUB_QOSC_AHB_REG_BWMON1_UPDATE_FLAG                 BIT(1)
#define BIT_PUB_QOSC_AHB_REG_BWMON0_UPDATE_FLAG                 BIT(0)

/* REG_PUB_QOSC_AHB_REG_BWMON0_WBW_CNT */

#define BIT_PUB_QOSC_AHB_REG_BWMON0_WBW_CNT(x)                  (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON0_RBW_CNT */

#define BIT_PUB_QOSC_AHB_REG_BWMON0_RBW_CNT(x)                  (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON1_WBW_CNT */

#define BIT_PUB_QOSC_AHB_REG_BWMON1_WBW_CNT(x)                  (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON1_RBW_CNT */

#define BIT_PUB_QOSC_AHB_REG_BWMON1_RBW_CNT(x)                  (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON2_WBW_CNT */

#define BIT_PUB_QOSC_AHB_REG_BWMON2_WBW_CNT(x)                  (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON2_RBW_CNT */

#define BIT_PUB_QOSC_AHB_REG_BWMON2_RBW_CNT(x)                  (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON3_WBW_CNT */

#define BIT_PUB_QOSC_AHB_REG_BWMON3_WBW_CNT(x)                  (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON3_RBW_CNT */

#define BIT_PUB_QOSC_AHB_REG_BWMON3_RBW_CNT(x)                  (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON4_WBW_CNT */

#define BIT_PUB_QOSC_AHB_REG_BWMON4_WBW_CNT(x)                  (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON4_RBW_CNT */

#define BIT_PUB_QOSC_AHB_REG_BWMON4_RBW_CNT(x)                  (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON5_WBW_CNT */

#define BIT_PUB_QOSC_AHB_REG_BWMON5_WBW_CNT(x)                  (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON5_RBW_CNT */

#define BIT_PUB_QOSC_AHB_REG_BWMON5_RBW_CNT(x)                  (((x) & 0xFFFFFFFF))

/* REG_PUB_QOSC_AHB_REG_BWMON_VOTE_CTRL */

#define BIT_PUB_QOSC_AHB_REG_BWMON_UPDATE_FLAG_DFS_CNT(x)       (((x) & 0x1F) << 8)
#define BIT_PUB_QOSC_AHB_REG_BWMON_VOTE_V3CPU_EN                BIT(5)
#define BIT_PUB_QOSC_AHB_REG_BWMON_VOTE_V3ACC_EN                BIT(4)
#define BIT_PUB_QOSC_AHB_REG_BWMON_VOTE_NRCPU_EN                BIT(3)
#define BIT_PUB_QOSC_AHB_REG_BWMON_VOTE_NRACC_EN                BIT(2)
#define BIT_PUB_QOSC_AHB_REG_BWMON_VOTE_MINIAP_EN               BIT(1)
#define BIT_PUB_QOSC_AHB_REG_BWMON_VOTE_APCPU_EN                BIT(0)


#endif /* PUB_QOSC_AHB_REG_H */


